Ultra low-power asynchronous-logic design for high variation-space and wide operation-space applications

This thesis pertains to the design of low-power/ultra low-power high variation-space and wide operation-space digital electronics for portable/mobile applications. High variation-space and wide operation-space respectively refer to error-free operation despite high variations in the prevailing conditions (including Process, Voltage and Temperature (PVT) variations) and under a wide range of activity levels or workload. In view of said spaces, we adopt the somewhat esoteric asynchronous-logic (async) vis-à-vis the conventional synchronous-logic (sync); more specifically, the Matched Delay (MD) and the Quasi-Delay-Insensitive (QDI). For an MD pipeline operating under a wide operation-space (alternating between active and idle), we propose a fine-grain power gating methodology (applicable to three different gating configurations) to reduce short-circuit and leakage wasted powers. By exploiting the 4-phase handshake protocol, the ensuing overhead of the proposed power gating is low, specifically one inverter (per pipeline stage) and <15% delay. For sake of robustness in view of the extreme/virtually intractable PVT in ultra low-power sub-threshold (sub-Vt) operation, where the circuit delay varies exponentially with PVT, we propose to adopt the QDI protocol. To quickly estimate to the first-order the delay variations (due to Vt, supply voltage (VDD) and temperature; thus the required delay safety margin) of digital circuits in sub-Vt, we propose and derive a set of simple yet insightful analytical equations. The derived equations are verified by simulations, and we show that they are accurate for first-order estimations (with an inconsequential worst-case error of