56 p.Consistent improvements in integrated circuit density and performance have been amply demonstrated over the past 20 years by using transistor scaling, a model for simultaneously improving transistor density, performance, functionality and cost per function. In the transistor scaling sub-micron technology, the fact showed that interconnect delay starts to dominate the gate delay. Copper was introduced as a primary interconnect material in integrated circuit in 1997 by IBM due to its lower resistivity than aluminum.Master of Science (Microelectronics
After four decades of continuous scaling on the CMOS technology, many innovations have been realized...
One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to att...
acute problem in the interconnect area as IC feature sizes continually scale below 32 nm. When the c...
Copper and low dielctric constantant (k) materials are poised to become the dominant interconnect sc...
The objective of this research is to present a holistic study of the on-chip copper interconnect tec...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic be...
textInterconnect scaling has given rise to serious reliability concerns under the impact of low k i...
Advancement of the current Two-Dimensional integrated circuits (2D-ICs) is limited by increasing int...
Abstract—A realistic assessment of future interconnect perfor-mance is addressed, specifically, by m...
L’évolution de la technologie microélectronique conduit à une densité d’intégration toujours plus fo...
The integration of Cu interconnections will require sophisticated structures to prevent Cu from comi...
The technological trend of shrinking integrated circuits in order to increase the logic density and ...
As the demand for wearable devices and mobile technology is increasing rapidly, a smaller but more p...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 20...
After four decades of continuous scaling on the CMOS technology, many innovations have been realized...
One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to att...
acute problem in the interconnect area as IC feature sizes continually scale below 32 nm. When the c...
Copper and low dielctric constantant (k) materials are poised to become the dominant interconnect sc...
The objective of this research is to present a holistic study of the on-chip copper interconnect tec...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic be...
textInterconnect scaling has given rise to serious reliability concerns under the impact of low k i...
Advancement of the current Two-Dimensional integrated circuits (2D-ICs) is limited by increasing int...
Abstract—A realistic assessment of future interconnect perfor-mance is addressed, specifically, by m...
L’évolution de la technologie microélectronique conduit à une densité d’intégration toujours plus fo...
The integration of Cu interconnections will require sophisticated structures to prevent Cu from comi...
The technological trend of shrinking integrated circuits in order to increase the logic density and ...
As the demand for wearable devices and mobile technology is increasing rapidly, a smaller but more p...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 20...
After four decades of continuous scaling on the CMOS technology, many innovations have been realized...
One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to att...
acute problem in the interconnect area as IC feature sizes continually scale below 32 nm. When the c...
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