Design of low drop-out linear voltage regulator

The study of power management systems has increased obviously in the past few years corresponding to the drastic increase in the use of battery powered portable devices. These power management systems usually contain several low dropout voltage regulators (LDO) with large load capacitors for the stability requirement. However, the large load capacitors cannot be integrated in these LDO devices in current CMOS technologies, so extra space will be occupied by these external load capacitors. In order to seek space saving and fulfill the requirements of the system-on-chip solutions in 0.18um technology, the capacitor-less LDO was designed in the final year project. However, performance issues like stability and transient response degradation would be encountered due to the reduction of load capacitance. Several design schemes were applied in the new compensation technique. In the design stage, stringent conditions were discussed to guarantee the LDO biased in the proper region (from 1.5V-3V). Meanwhile, transfer functions were also derived to verify the deduction. Lastly, by applying the fast sense path with essential components like OTA and differentiator, these performance obstacles had been ideally improved. Finally, the compensation technique was implemented and verified in Cadence. The simulation results (PM≈90℃, Settling Time < 10us, etc.) proved the performance issues had been overcome in practical. Besides, comparisons were done between different corner models to ensure the LDO working properly in real manufacturing. Though there were still some problems, the performance of the compensated capacitor-less LDO would not be affected.Bachelor of Engineerin