Building-block design for a high switching frequency DC-DC converter IC

This Final Year Project pertains to the design and verification of building blocks of a high switching-frequency DC-DC Buck converter. The said building blocks are a digital controller, a proposed novel Reverse-Current Sense and Stop feedback circuit (RCSS), and a proposed novel Zero-Voltage-Switching (ZVS) circuit. The digital controller implements a digital compensation algorithm to correct the error in the output voltage. This project continues the work done in the last year’s Final Year Project by verifying the previously designed digital controller using computer simulations. The simulation results show that the digital controller works correctly. The proposed RCSS mitigates the undesirable reverse-current loss from the load. The RCSS comprises a voltage comparator, a current-sensor, and a digital control logic circuit. The voltage comparator of the RCSS is designed using CMOS 0.18 m process. Simulation results show that the comparator has a maximum speed of 120 MHz, and average power dissipation of 363 W. Simulation results show that the reverse-current reduction by the RCSS results in an average load-power of 47 mW (at the discontinuous conduction mode for low-power operation) that translates to 16 % power efficiency improvement when compared to that of a conventional Buck converter (with a conventional feedback); both circuits operate at 5 MHz switching-frequency, 1.8 V supply voltage for the comparator, 3.3 V supply voltage for the other components, 2 V output voltage and 23.5 mA load current. The proposed ZVS circuit introduces deliberate delays at rising and falling edges of the output pulses to further reduce power dissipation. Simulation results show that the DC-DC converter with both the proposed RCSS and the proposed ZVS circuit achieves a 12 % power efficiency improvement (an average load-power of 39 mW) when compared to that of the DC-DC converter with just the proposed RCSS.Bachelor of Engineerin