On the Low-Frequency Noise Characterization of Z2-FET Devices

This paper addresses the low-frequency noise characterization of Z2-FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although other applications, as for example electro static discharge (ESD) protection, have been reported. The experimentally extracted power spectral density of current reveals that the high-diode series resistance, carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field. A simple model considering the contribution of the main noise sources is proposed.This work was supported in part by the European REMINDER 687931 Grant, in part by the Consejeria de Economia, Conocimiento, Empresas y Universidad de la Junta de Andalucia and European Regional Development Fund (ERDF), under Grant SOMM17/6109/ UGR, and in part by the TEC2017-89800-R Project