Characterization and fabrication of 90nm strained silicon PMOS using TCAD

The paper focuses on the enhancement of conventional 90nm PMOS using graded silicon germanium layer (SiGe) within the channel and bulk of semiconductor. The performance of conventional 90nm PMOS and 90nm PMOS with silicon germanium layer was compared. A process simulation of Strained Silicon PMOS and its electrical characterization was done using Silvaco TCAD tool. The analysis focused on Id-Vg and Id-Vd characteristic, and hole mobility changes. With the Germanium concentration of 35%, the threshold voltage Vt for the strained Si and conventional PMOS is -0.228035V and - 0.437378V respectively. This indicates that the strained silicon had lower power consumption. In addition, the output characteristics obtained for Strain Silicon PMOS showed an improvement of the drain current as compared with conventional PMOS