An energy efficient xor gate implementation resistant to power analysis attacks

Exclusive-OR (XOR) operation plays an important role in the hardware implementation of many cryptographic algorithms. Since the hardware implementation of XOR gate is vulnerable to side channel analysis such as power analysis attacks, efficient countermeasures are required. The existing approaches provide countermeasures by placing more number of transistors at key locations in the gate implementation so as to make it resilient to power analysis attacks. But, the induction of more number of transistors increases both silicon area as well as energy dissipation of the gate. In this work, an energy efficient structure is proposed for XOR gate implementation to thwart power analysis attacks. The proposed differential structure uses adiabatic logic style to achieve low energy consumption and the power analysis resistance is obtained through proper charge sharing mechanisms. The power analysis resistance is evaluated by analyzing two statistical parameters, namely Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD). Our proposed XOR gate implementation gives least values of NED and NSD when compared to the existing implementations thus proving that the proposed implementation is a more efficient countermeasure to thwart power analysis attacks