Defect-oriented test and design-for-testability technique for resistive random access memory

Resistive Random Access Memory (ReRAM) is one of the main emerging memories that has great potential to replace existing semiconductor memories. However, it cannot be denied that ReRAM prone to have defects that lead to test escape and reliability problems. Bridge defects that occurred in the memory array might cause Undefined State Faults (USFs) during read operation. USFs cause the faulty ReRAM cell difficult to be set to the desired logical value. Hence, this paper proposed a design-for-test (DfT) technique, namely Adaptive Sensing Read Voltage (ASRV) to detect the USFs that arise during three types of bridge defects injection. For this study, a faulty ReRAM was used to be tested during simulation using Silvaco EDA simulation tools and implementation of defect-oriented test. A DfT circuitry is added in the existing sense amplifier so that this memory device can operate during the normal mode and testing mode. Based on the simulation result, the proposed DfT technique will be able to detect the USFs