An Architecture for a reconfigurable charge-summation based ADC

Presented in this paper is a low power, area efficient reconfigurable analog-to-digital (ADC) converter, utilising a charge-summation technique with a switched-capacitor implementation. Using a non-inverting switched-capacitor integrator a staircase ramp is produced using switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a reconfigurable ADC for use in a reconfigurable radio