Measurement and numerical analysis of C-V characteristics for normally-on SiCED-JFET

In this paper, terminal capacitances of a normally-on SiCED-JFET are measured, analyzed and simulated. All these capacitances are measured using an auto-balanced (guarded) capacitance test-bench that leads to the standard 3-terminal model capacitors CGS, CDS and CGD. This test bench is developed to measure each capacitance individually, without any mutual influence. 2D finite-element simulations are used to show that the capacitance CGD cannot be modeled by a standard planar junction model. This is due to the influence of two dimensional effects around the buried layer P+. A new analytical model of CGD is proposed. A good agreement is obtained between simulations and measurements of the different capacitances