Modeling of metal-ferroelectric-insulator-semiconductor structure considering the effects of interface traps

An improved model, in which the interface traps effects are considered, is developed by combining with quantum mechanical model, dipole switching theory and silicon physics of metal-oxide-semiconductor structure to describe the electrical properties of metal-ferroelectric-insulator-semiconductor (MFIS) structure. Using the model, the effects of the interface traps on the surface potential (ϕSi) of the semiconductor, the low frequency (LF) capacitance-voltage (C-V) characteristics and memory window of MFIS structure are simulated, and the results show that the ϕSi- V and LF C-V curves are shifted toward the positive-voltage direction and the memory window become worse as the density of the interface trap states increases. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the improved model can be integrated into electronic design automation (EDA) software for circuit simulation