Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios

All electronic processing components in future deep nanotechnologies will exhibit high noise level and/or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. Systems implemented with these devices would exhibit a high probability to fail, causing an unacceptably reduced reliability. In this paper we introduce an innovative input and output data redundancy principle for sequential block circuits, the responsible to keep the state of the system, showing its efficiency in front of other robust technique approaches. The methodology is totally different from the Von Neumann approaches, because element are not replicated N times, but instead, they check the coherence of redundant input data no allowing data propagation in case of discrepancy. This mechanism does not require voting devices