Reconfigurable systems have been shown to achieve significant performance speedup through architectures that map the most time-consuming application kernel modules or inner loops to a reconfigurable datapath. As each portion of the application starts to execute, the system partially reconfigures the datapath so as to perform the corresponding computation. The reconfigurable datapath should have as few and simple hardware blocks and interconnections as possible, in order to reduce its cost, area, and reconfiguration overhead. To achieve that, hardware blocks and interconnections should be reused as much as possible across the application. We represent each piece of the application as a data-flow graph (DFG). The DFG merging process identifie...
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-...
Abstract — Hardware accelerators integrating to general pur-pose processors (GPPs) are increasingly ...
International audienceDynamic reconfiguration of hardware resources is increasingly used in applicat...
High latencies in FPGA reconfiguration are known as a major overhead in run-time reconfigurable syst...
Hardware specialization is often the key to efficiency for programmable embedded systems, but comes ...
During the last years, the computing performance increased for basically all integrated digital circ...
By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. ...
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application ru...
The rising complexity, customization and short time to market of modern digital systems requires aut...
The increased power densities of deep submicron process technologies have made on-chip temperature t...
International audienceThis paper introduces and assesses a new technique to minimize the memory foot...
This research examines the role of dynamically reconfigurable logic in systems-on-a-chip (SOC) desig...
Due to limits in technology scaling, energy efficiency of logic devices is decreasing in successive...
Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-...
Timothy J. Callahan and John Wawrzynek University of California--Berkeley Widespread acceptance of F...
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-...
Abstract — Hardware accelerators integrating to general pur-pose processors (GPPs) are increasingly ...
International audienceDynamic reconfiguration of hardware resources is increasingly used in applicat...
High latencies in FPGA reconfiguration are known as a major overhead in run-time reconfigurable syst...
Hardware specialization is often the key to efficiency for programmable embedded systems, but comes ...
During the last years, the computing performance increased for basically all integrated digital circ...
By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. ...
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application ru...
The rising complexity, customization and short time to market of modern digital systems requires aut...
The increased power densities of deep submicron process technologies have made on-chip temperature t...
International audienceThis paper introduces and assesses a new technique to minimize the memory foot...
This research examines the role of dynamically reconfigurable logic in systems-on-a-chip (SOC) desig...
Due to limits in technology scaling, energy efficiency of logic devices is decreasing in successive...
Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-...
Timothy J. Callahan and John Wawrzynek University of California--Berkeley Widespread acceptance of F...
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-...
Abstract — Hardware accelerators integrating to general pur-pose processors (GPPs) are increasingly ...
International audienceDynamic reconfiguration of hardware resources is increasingly used in applicat...