Mpsocbench: A Toolset For Mpsoc System Level Evaluation

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Recent design methodologies and tools aim at enhancing the design productivity by providing a software development platform before defining the final MPSoC architecture details. However, the simulation can only be efficiently performed when using a modeling and simulation engine that supports the system behavior description in a high abstraction level. The lack of MPSoC virtual platform prototyping integrating both scalable hardware and software in order to create and evaluate new methodologies and tools motivated us to develop MPSoCBench. This toolset is a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with 1, 2, 4, 8, 16, 32, or 64 cores, cross-compilers, IPs, interconnections, and 17 parallel version of software from well-known benchmarks. This tool also provides power consumption estimation for MIPS and SPARC processors. The MPSoCBench sums 864 different configurations automated through scripts.164171CAPES; Coordenação de Aperfeiçoamento de Pessoal de Nível Superior; FAPESP; Coordenação de Aperfeiçoamento de Pessoal de Nível SuperiorFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)(2012) IEEE Std 1666TM Standard SystemC Language Reference Manual, , IEEE Computer Society JanuaryAzevedo, R., Rigo, S., Bartholomeu, M., Araujo, G., Araujo, C., Barros, E., The archc architecture description language and tools (2005) International Journal of Parallel Programming, 33 (5), pp. 453-484. , OctoberBenini, L., Bertozzi, D., Menichelli, F., Olivieri, M., MPARM: Exploring the multi-Processor SoC Design space with system C (2005) Journal of VLSI Signal Processing, 41, pp. 169-182Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Wood, D.A., (2011) The gem5 Simulator, 39, pp. 1-7Boukhechem, S., Bourennane, E., Samahi, A., Co-simulation platform based on system C for multiprocessor system on chip architecture exploration (2007) Proceedings of IEEE International Conference on Microelectronics (ICM)Guedes, M., Auler, R., Duenha, L., Borin, E., Azevedo, R., An automatic energy consumption characterization of processors using ArchC (2013) Journal of Systems Architecture, , JuneGuthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B., MiBench: A free, commercially representative embedded benchmark suite (2001) Proceedings of IEEE 4th Annual Workshop on Workload Characterization, Held in Conjunction with the 34th Annual IEEE/ACM, pp. 03-14. , DecemberIqbal, S.M.Z., Liang, Y., Grahn, H., ParMiBench: An Open-Source benchmark of embedded multiprocessor systems (2010) IEEE Computer Architecture Letters, 9 (2), pp. 45-48Klein, F., Araujo, G., Azevedo, R., Leao, R., Santos, L., An efficient framework for high-Level power exploration (2007) Proceedings of the 50th Midwest Symposium on Circuits and Systems-MWSCAS, pp. 1046-1049. , AugustLeupers, R., Temam, O., (2010) Processor and System-on-Chip Simulation, , Springer New YorkMagnusson, P., Virtutech, M.C., Forsgren, J.E.D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., Werner, B., (2002) Simics: A Full System Simulation Platform, 35Mello, A., Maia, I., Greiner, A., Pecheux, F., Parallel simulation of systemC TLM 2.0 Compliant MPSoC on SMP workstations (2010) Proceedings of Design, Automation and Test in Europe-DATE, pp. 606-609. , MarchMoraes, F., Calazans, N., Mello, A., Möller, L., Ost, L., (2004) Hermes: An Infrastructure for Low Area Overhead Packet-switching Networks on Chip, 38, pp. 69-93. , Elsevier Science Publishers B. V., Amsterdam, The Netherlands, The Netherlands, OctPaulin, P., Pilkington, C., Langevin, M., Bensoudane, E., Lyonnard, D., Benny, O., Lavigueur, B., Nicolescu, G., Parallel programming models for a multiprocessor SoC Platform applied to networking and multimedia (2006) Proceedings of IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14 (7). , JulyWoo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A., The splash-2 Programs: Characterization and methodological considerations (1995) Proceedings of the 22nd International Symposium on Computer Architecture-ISCA'95, pp. 24-36. , AC