Using Multiple Abstraction Levels To Speedup An Mpsoc Virtual Platform Simulator

Virtual platforms are of paramount importance for design space exploration and their usage in early software development and verification is crucial. In particular, enabling accurate and fast simulation is specially useful, but such features are usually conflicting and tradeoffs have to be made. In this paper we describe how we integrated TLM communication mechanisms into a state-of-the-art, cycle-accurate, MPSoC simulation platform. More specifically, we show how we adapted ArchC fast functional instruction set simulators to the MPARM platform in order to achieve both fast simulation speed and accuracy. Our implementation led to a much faster hybrid platform, reaching speedups of up to 2.9 and 2.1x on average with negligible impact on power estimation accuracy (average 3.26% and 2.25% of standard deviation). © 2011 IEEE.99105 Institution of Electrical Engineers (IEEE) Reliability Society,Karlsruhe Institute of Technology (KIT)Benini, L., Bertozzi, D., Bogliolo, A., Menichelli, F., Olivieri, M., MPARM: Exploring the multi-processor SoC design space with systemC (2005) Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 41 (2), pp. 169-182. , DOI 10.1007/s11265-005-6648-1Chen, J., Dubois, M., Stenstrom, P., Integrating complete-system and user-level performance/power simulators: The simwattch approach (2003) ISPASS '03: Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 1-10Rigo, S., Araujo, G., Bartholomeu, M., Azevedo, R., ArchC: A SystemC-based architecture description language (2004) Proceedings - Symposium on Computer Architecture and High Performance Computing, pp. 66-73. , Proceedings - 16th Symposium on Computer Architecture and High Performance ComputingBlack, D.C., Donovan, J., (2004) SystemC: From the Ground UpDales, M., (2003), www.cl.cam.ac.uk/mwd24/phd/swarm.html, FebruaryLoghi, M., Poncino, M., Benini, L., Cycle-accurate power analysis for multiprocessor systems-on-a-chip (2004) GLSVLSI '04: Proceedings of the 14th ACM Great Lakes Symposium on VLSI, pp. 410-406Ferri, C., Moreshet, T., Bahar, R.I., Benini, L., Herlihy, M., A hardware/software framework for supporting transactional memory in a mpsoc environment (2007) SIGARCH Comput. Archit. News, 35 (1), pp. 47-54Baldassin, A., Klein, F., Araujo, G., Azevedo, R., Centoducatte, P., Characterizing the energy consumption of software transactional memory (2009) Computer Architecture Letters, 8 (2), pp. 56-59. , FebMagnusson, P.S., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Werner, B., Simics: A full system simulation platform (2002) Computer, 35, pp. 50-58Brooks, D.M., Bose, P., Schuster, S.E., Jacobson, H., Kudva, P.N., Buyuktosunoglu, A., Wellman, J.-D., Cook, P.W., Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors (2000) IEEE Micro, 20 (6), pp. 26-44. , DOI 10.1109/40.888701Austin, T., Larson, E., Ernst, D., Simplescalar: An infrastructure for computer system modeling (2002) Computer, 35 (2), pp. 59-67Azevedo, R., Rigo, S., Bartholomeu, M., Araujo, G., Araujo, C., Barros, E., The ArchC architecture description language and tools (2005) International Journal of Parallel Programming, 33 (5), pp. 453-484. , DOI 10.1007/s10766-005-7301-0Ghenassia, F., (2006) Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded SystemsCao Minh, C., Chung, J., Kozyrakis, C., Olukotun, K., STAMP: Stanford transactional applications for multi-processing (2008) IISWC '08: Proceedings of the IEEE International Symposium on Workload Characterization, , Septembe