Capacitive-sar Adc Input Offset Reduction By Stray Capacitance Compensation

A 10-bit, 80-kS/s charge-redistribution successive approximation analog-to-digital converter is presented, which incorporates a novel stray capacitance compensation technique that is appropriate for low-power design in order to accomplish input voltage offset reduction. Three different versions of the ADC were fabricated in 0.35 m, 4M2P standard CMOS process. The compensation mechanism implemented in one of the ADC versions proved its effectiveness by showing an input voltage offset that is circa 60 times smaller than what was measured in the other two uncompensated versions. Also from fabricated samples of the compensated ADC, measured values for INL and DNL are 0.47 LSB and 0.58 LSB, respectively. Operating at 3.3V at the nominal speed, the offset-compensated ADC consumes 122 W. ©2008 IEEE.Mortezapour, S., Lee, E.K.F., A 1-V, 8-bit successive approximation ADC in standard CMOS process (2000) IEEE J. Solid-State Circuits, 35, p. 642. , AprNeubauer, H., Desel, T., Hauer, H., A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 (2001) Proc. 8th IEEE Int. Conf. Electronics, Circuits and Systems, p. 859. , SepFayomi, C.J.B.Roberts, G.W.Sawan, M., A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 μm CMOS technology, Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , 1, no., pp.460-463 1, 6-9 May 2001Promitzer, G., 12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s, Solid-State Circuits, IEEE Journal of, 36, no.7, pp.1138-1143, Jul 2001Kuttner, F., A 1.2 V 10b 20 MSample/s non-binany successive approximation ADC in 0.13 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech, p. 136. , Papers, 2002, pSauerbrey, J., Schmitt-Landsiedel, D., Thewes, R., A 0.5-V 1μW successive approximation ADC (2003) IEEE J. Solid-State Circuits, 38, p. 1261. , JulScott, M.D., Boser, B.E., Pister, K.S.J., An ultralow-energy ADC for smart dust (2003) IEEE J. Solid-State Circuits, 38, p. 1123. , JulLin, C.-S., Liu, B.-D., A new successive approximation architecture for low-power low-cost CMOS A/D converter (2003) IEEE J. Solid-State Circuits, 38, p. 54. , JanCulurciello, E., Andreou, A., An 8-bit, 1 mW successive approximation ADC in SOI CMOS (2006) IEEE Trans. Circuits Syst. II, Expr. Briefs, 53, p. 858. , SepHao-Chiao HongGuo-Ming Lee, A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC, Solid-State Circuits, IEEE Journal of , 42, no.10, pp.2161-2168, Oct. 2007Abdelhalim, K.MacEachern, L.Mahmoud, S., A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications, Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , no., pp.2351-2354, 27-30 May 2007Verma, N.Chandrakasan, A.P., An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes, Solid-State Circuits, IEEE Journal of , 42, no.6, pp.1196-1205, June 2007Gregorian, R., Martin, K.W., Temes, G.C., Switched-capacitor circuit design (1983) Proceedings of the IEEE, 71 (8), pp. 941-966. , AugHastings, A., (2001) The Art of Analog Layout, , New Jersey: Prentice-HallEichenberger, C., Guggenbuhl, W., On charge injection in analog MOS switches and dummy switch compensation techniquesRossi, A., Fucili, G., Nonredundant successive approximation register for A/D converters (1996) Electronics Letters, 32 (12), pp. 1055-1057. , 6 JunIEEE Std. 1057-1994, IEEE standard for digitizing waveform records, The Institute of Electrical and Electronics Engineers, New York, 199