Multi-dimensional Evaluation Of Haswell's Transactional Memory Performance

This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. This study evaluates the strengths and weaknesses of this new architecture exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench [1] and the CLOMP-TM [2] benchmarks. This detailed performance study provides insights on the constraints imposed by the Intel's Transaction Synchronization Extension (Intel's TSX) and introduces a simple, but efficient policy for guaranteeing forward progress on top of the besteffort Intel's HTM and also was critical to achieving performance. The evaluation also shows that there are a number of potential improvements for designers of TM applications and software systems that use Intel's TM and provides recommendations to extract maximum benefit from the current TM support available in Haswell.144151NSERC; Natural Sciences and Engineering Research Council of CanadaHong, S., Oguntebi, T., Casper, J., Bronson, N., Kozyrakis, C., Olukotun, K., Eigenbench: A simple exploration tool for orthogonal TM characteristics (2010) The IEEE International Symposium on Workload Characterization (IISWC), pp. 1-11. , DecSchindewolf, M., Bihari, B., Gyllenhaal, J., Schulz, M., Wang, A., Karl, W., What scientific applications can benefit from hardware transactional memory? (2012) Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, pp. 901-9011. , ser. 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