Modeling and Simulation of D Flip-Flop using MTCMOS Technique

In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected any more. The current use of multi-Vt to control leakage power targets combinational gates, even though sequential elements such as flip flops also contribute appreciable leakage. In this paper low power, high speed design of D flip flop is enumerated. Numerous techniques are utilized to minimize sub-threshold leakage power as well as the power consumption of the CMOS circuits. The proposed circuit in this paper shows a design for D flip flop to increase overall speed of the circuit as compared to other circuits by using minimum number of transistors to achieve lowest power consumption. This paper proposes four leakage reduction techniques such as leakage feedback; gate-length biasing, dual threshold techniques and MTCMOS for use in D flip flop. This work analyses the leakage- current and power of different implementation of D flip flop using transmission gate. All the designs are simulated using Cadence in 45nm process technology. Simulation result shows that the proposed MTCMOS based D flip flop has the least leakage power dissipation