Statistical Variability in 5 nm Vertically Stacked Lateral Si Nanowire Transistors

In this work, we present a comprehensive computational study of the impact of the principle sources of statistical variability, i.e., random dopant fluctuations, wire edge roughness, and metal gate granularity, on the threshold voltage, drain-induced barrier lowering, and drive current. Furthermore, we investigated the position dependent performance and geometrical variation of the lateral nanowires in the stack as new sources of process variability