Statistical variability and reliability and the impact on corresponding 6T-SRAM cell design for a 14-nm node SOI FinFET technology

This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness, metal-gate granularity and random interface trapped charges in N/PBTI are considered