Effect of Interface State Trap Density on the Performance of Scaled Surface Channel In0.3Ga0.7As MOSFETs

The effect of interface state trap density, D-it, on the I-D-V-G characteristics of scaled surface channel MOSFETs based on In0.3Ga0.7As channel has been investigated using drift-diffusion simulations. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current when these devices are scaled from a gate length of 65 nm to 35 nm, 25 nm and 18 nm. The distributions of interface states having high density tails that extend into the conduction band can significantly impact the subthreshold performance of the larger gate length device. Furthermore, the same distributions have smaller impact on the performance of shorter channel devices which were designed with smaller high-kappa thicknes