A dynamically reconfigurable hardware co-processor for a multi-standard wireless MAC processor

The dynamically reconfigurable MAC processor is an innovative architecture specialized for the wireless MAC layer, and aimed at consumer hand-held devices. It is a software/hardware partitioned platform where the microprocessor uses a reconfigurable hardware co-processor to delegate critical tasks. This allows the microprocessor to handle fast and complex MAC protocols while clocking at relatively slow speeds, thus consuming less power. The architecture on the whole is designed to be dynamically reconfigurable. It will handle data streams of multiple (up to 3) different protocol standards, by reconfiguring on a packet-by-packet basis. Results of simulation of packet transmission and reception on a prototype Simulink model indicate that a packet to packet reconfiguration for three concurrent data streams, while meeting protocol real-time requirements, will indeed be possible