Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors

This article describes a process flow that has enabled the first demonstration of functional, fully self-aligned 100 nm enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-kappa dielectric, Pt/W as metal gate stack, and SiN as sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. Encouraging data are presented for 100 nm gate length devices including threshold voltage of 0.32 V, making these the shortest, fully self-aligned gate length enhancement mode III-V MOSFETs reported to date. This work is a significant step forward to the demonstration of high performance "siliconlike" III-V MOSFETs