Scalable, security-oriented solutions for nanoCMOS electronics

The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS – www.nanocmos.ac.uk) has been funded to tackle some of the challenges facing the semiconductor electronics industry caused by the progressive scaling of CMOS transistors. As transistor dimensions are now at the nanometer scale with 40nm MOSFETs already in mass production and sub-10 nm transistors scheduled for production by 2018, the intrinsic parameter fluctuations caused by the inherent discreteness of charge and matter at this atomistic scale are now one of the major challenges that the semiconductor electronics industry needs to address. The variability at the device level affects profoundly the circuit/system design process and hence can be regarded a semiconductor industry-wide problem. Fortunately many of the statistical variability related issues can be understood and forecasted through large scale simulation of ensembles of potentially hundreds of thousands of atomistically varying devices. However, one of the main distinguishing features of NanoCMOS when compared to other high performance computing (HPC) simulation domains is the imperative requirements on fine grained security. The data, the designs and even the simulations themselves all potentially have highly sensitive commercial intellectual property (IP) value associated with them, ranging from the IP of device manufacturers and the design houses through to licenses needed to run simulation and design software. This paper outlines the e-Infrastructure that has been developed within the nanoCMOS project with specific focus upon the security capabilities it supports and how these address the IP protection requirements of the industrial and collaborating partners. Our ultimate goal is to provide an environment that addresses security across the board and scales to meet the HPC and data management requirements of nanoCMOS research