Although directory-based write-invalidate cache coherence protocols have a potential to improve the performance of large-scale multiprocessors, coherence misses limit the processor utilization. Therefore, so-called competitive-update protocols-hybrid protocols that on a per-block basis dynamically switch between write-invalidate and write-update-have been considered as a means to reduce the coherence miss rate and have been shown to be a better coherence policy for a wide range of applications. Unfortunately, such protocols may cause high traffic peaks for applications with extensive use of migratory objects. These traffic peaks can offset the performance gain of a reduced miss rate if the network bandw...
The coherence protocol is a first-order design concern in multicore designs. Directory protocols are...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Journal ArticleFor a parallel architecture to scale effectively, communication latency between proce...
Although directory-based write-invalidate cache coherence protocols have a potential to improve the ...
Cache coherence protocols for shared-memory multiprocessors use invalidations or updates to maintain...
Invalidation-based cache coherence protocols have been extensively studied in the context of large-s...
A number of different systems (multiprocessor systems, distributed systems, and nowadays Internet) r...
Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to ac...
[[abstract]]An optimization scheme for a directory-based cache coherence protocol for multistage int...
Since data access patterns vary from application to application, neither write-invalidate nor write-...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
Click on the DOI link to access the article (may not be free).While addressing cache coherency in sh...
Cache coherence protocols play an important role in the performance of distributed and centralized s...
In this paper we present simulation algorithms that characterize the main sources of communication g...
The speed of processors increases much faster than the memory access time. This makes memory accesse...
The coherence protocol is a first-order design concern in multicore designs. Directory protocols are...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Journal ArticleFor a parallel architecture to scale effectively, communication latency between proce...
Although directory-based write-invalidate cache coherence protocols have a potential to improve the ...
Cache coherence protocols for shared-memory multiprocessors use invalidations or updates to maintain...
Invalidation-based cache coherence protocols have been extensively studied in the context of large-s...
A number of different systems (multiprocessor systems, distributed systems, and nowadays Internet) r...
Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to ac...
[[abstract]]An optimization scheme for a directory-based cache coherence protocol for multistage int...
Since data access patterns vary from application to application, neither write-invalidate nor write-...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
Click on the DOI link to access the article (may not be free).While addressing cache coherency in sh...
Cache coherence protocols play an important role in the performance of distributed and centralized s...
In this paper we present simulation algorithms that characterize the main sources of communication g...
The speed of processors increases much faster than the memory access time. This makes memory accesse...
The coherence protocol is a first-order design concern in multicore designs. Directory protocols are...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Journal ArticleFor a parallel architecture to scale effectively, communication latency between proce...