A Soft Error Study on Tri-gate based FinFET and Junctionless-FinFET 6T SRAM Cell – A Comparison

This paper is under in-depth investigation due to suspicion of possible plagiarism on a high similarity index When junction based semiconductor devices are scaled down to extreme lower dimensions, the formation of ultra-sharp junctions between source/drain and channel becomes complex since the doping concentration has to vary by several orders of magnitudes over a distance of a few nanometers. In addition, As CMOS device is scaling down significantly, the sensitivity of Integrated Circuits (ICs) to Single Event Upset (SEU) radiation increases. As soft errors emerge as reliability threat there is a significant interest lies both at device and circuit level for SEU hardness in memories. The critical dose observed in FinFET and Junctionless-FinFET (JLT) based 6T-SRAM is given by LET = 1.4 and 0.1 pC/µm. The simulation result analyzes electrical and SEU radiation parameters of FinFET and JLT based 6T-SRAM memory circuit