This paper introduces a framework that tackles the costs in area and energy consumed by methodologies like spatial or temporal redundancy with a different approach: given an algorithm, we find a transformation in which part of the computation involved is transformed into memory accesses. The precomputed data stored in memory can be protected then by applying traditional and well established ECC algorithms to provide fault tolerant hardware designs. At the same time, the transformation increases the performance of the system by reducing its execution time, which is then used by customized software-based fault tolerant techniques to protect the system without any degradation when compared to its original form. Application of this technique to...
We present a new approach to fault tolerance for High Performance Computing system. Our approach is ...
Abstract–Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundanc...
Today's computer architectures and semiconductor technologies are facing major challenges making the...
This paper describes a single-version algorithmic approach to design in fault tolerant computing in ...
In this dissertation we address the overhead reduction of fault tolerance (FT) techniques. Due to te...
As late-CMOS process scaling leads to increasingly variable circuits/logic and as most post-CMOS tec...
As machines increase in scale, it is predicted that failure rates of supercomputers will correspondi...
. Fault-tolerant programs are typically not only difficult to implement but also incur extra costs i...
Abstract. Fault-tolerant programs are typically not only difficult to implement but also incur extra...
Over the last years, an increasing number of safety-critical tasks have been demanded for computer s...
The paper describes a systematic approach for automatically introducing data and code redundancy int...
We present a formal approach to implement fault-tolerance in real-time embedded systems. The initial...
This paper describes how to design low-cost reliable computing software for various application syst...
Software-based fault tolerance techniques are a low-cost way to protect processors against soft erro...
Some of the present day applications run on computer platforms with large and inexpensive memories, ...
We present a new approach to fault tolerance for High Performance Computing system. Our approach is ...
Abstract–Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundanc...
Today's computer architectures and semiconductor technologies are facing major challenges making the...
This paper describes a single-version algorithmic approach to design in fault tolerant computing in ...
In this dissertation we address the overhead reduction of fault tolerance (FT) techniques. Due to te...
As late-CMOS process scaling leads to increasingly variable circuits/logic and as most post-CMOS tec...
As machines increase in scale, it is predicted that failure rates of supercomputers will correspondi...
. Fault-tolerant programs are typically not only difficult to implement but also incur extra costs i...
Abstract. Fault-tolerant programs are typically not only difficult to implement but also incur extra...
Over the last years, an increasing number of safety-critical tasks have been demanded for computer s...
The paper describes a systematic approach for automatically introducing data and code redundancy int...
We present a formal approach to implement fault-tolerance in real-time embedded systems. The initial...
This paper describes how to design low-cost reliable computing software for various application syst...
Software-based fault tolerance techniques are a low-cost way to protect processors against soft erro...
Some of the present day applications run on computer platforms with large and inexpensive memories, ...
We present a new approach to fault tolerance for High Performance Computing system. Our approach is ...
Abstract–Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundanc...
Today's computer architectures and semiconductor technologies are facing major challenges making the...