Logic and physical synthesis of cell arrays

This paper presents a logic and physical synthesis to achieve logic and geometric regularity. The logic synthesis can generate logic networks with reduced fan-out and can reduce the average length of interconnections when implemented over a cell matrix layout. The geometric regularity is reached by the use of a matrix composed by a set of basic cells. The implementation repeats some patterns and reflects the logic diagram structure. It make possible to generate automatically some layouts with a direct mapping from an OrBDD description and the entire routing is done over-the-cell. The main advantage of OrBDD logic description is to obtain layouts with an average fan-out twice smaller than with a synthesis from a SIS description. Moreover, this technique reduces 20% the average wire length