Effects of and Mitigation Strategies for Fast Voltage Transients on Current and Future FPGAs

As FPGAs grow in size and speed, so too does their power consumption. Power reduction techniques such as dynamic voltage scaling and clock gating can potentially be applied to FPGAs, however, it is unclear whether they are safe in the presence of fast voltage transients caused by large changes in on-chip signal activity. We measure the impact transients have on applications and present a mitigation strategy to prevent them from causing timing failures. We create transient generators that can significantly reduce an application's measured maximum frequency, by up to 25%. We also show that transients are very fast and hence transient mitigation must occur within the same clock cycle as the transient. We create a clock edge suppressor that detects a transient event and delays the next clock edge to prevent timing failure. Additionally, we present new architectures that would make future FPGAs more robust to voltage transients.M.A.S