Datacenter-optimized FPGAs

Large-scale deployment of field-programmable gate arrays (FPGAs) into datacenters has introduced new use cases that utilize the FPGA as a multi-user compute platform, require more on-chip memory, and can benefit even more from efficient hard blocks. Since FPGAs are not designed for this new use case, the burden of efficiently utilizing existing FPGAs for datacenter applications is on datacenter service providers and application designers. We propose to reduce this burden by optimizing the architecture of FPGAs to be more efficient for the emerging datacenter applications and create computer-aided design (CAD) tools that facilitate architecture modifications of FPGAs in general. In this thesis, we first create a CAD tool capable of automatic block RAM (BRAM) modelling and optimization for SRAM and MTJ memory technologies. We use this CAD tool to quantify the benefits of MTJ memory technology in BRAM design at both the block and system levels. In addition, we introduce COFFE 2, an automatic circuit modelling tool for heterogeneous FPGAs capable of accurately modelling arbitrary heterogeneous blocks using a proper mix of full custom and standard cell design flows. In addition, COFFE 2 can model complex fracturable logic tiles enhanced with hard arithmetic and can automatically floorplan them similarly to industrial practice. Next, we investigate virtualized FPGA designs that are more efficient at distributing data to one or more applications both in current FPGAs and in hard network-on-chip-enhanced FPGAs. Finally, we quantify the costs of keeping user data confidential against different threat levels in virtualized FPGAs, both in current FPGAs and in new architectures that we propose.Ph.D