Memory and Network Interface Virtualization for Multi-Tenant Reconfigurable Compute Devices

Field Programmable Gate Arrays (FPGAs) have increasingly been deployed in datacenters. These devices have proven effective at performing certain compute tasks better (faster, lower latency, higher throughput, and/or more efficiently) than traditional compute devices. In this work, we explore the application of the virtualization concept to multi-tenant FPGAs, with a specific focus on enabling multiple applications to securely share an FPGA and preventing snooping and/or errant behaviour. Conceptually, the traditional shell concept in FPGA design is extended to the hard shell and soft shell components. The hard shell focuses on the logical isolation of hardware applications on the same FPGA. For memory and networking interfaces on the FPGA, this work introduces hardware components aimed at enabling this isolation. In particular, the design of a new component that is termed the Network Management Unit (NMU) is presented in detail. The NMU enables the isolation of network traffic.M.A.S