Memory Architecture Optimization for Streaming Applications in High-Level Synthesis

FPGA designs have an immense design space, and there can be an order of magnitude performance difference between a naive and an optimized implementation. To optimize memory, the programmer faces the burden of a large number of iterative manual optimizations to achieve high performance. Motivated by this challenge, the goal of this work is to make memory optimizations easier to achieve. We present two frameworks 1) a buffer-to-BRAM mapping tool called MPack, and 2) a library of Stream Memory Components (SMCs). MPack optimizes the mapping of application buffers to FPGAâ s on-chip physical memories (BRAMs). One of the key challenges is the mismatch between the dimensions (bit width and depth) of application buffers and FPGAâ s on-chip physical memories, which leads to low memory utilization. We automate the process of grouping buffers together and implementing them as a single memory. We use a simulated annealing-based algorithm that analyzes buffer dimensions and throughput and automatically generates a memory solution such that the throughput is maximized for a given BRAM budget. The SMC library contains three types of SMCs that implement data transformations, frequently implemented by programmers manually: 1) stencil, 2) transpose, and 3) tiling. The SMCs can be optimized through our custom library API. The SMC can be configured to stream data directly between OpenCL kernels, as well as off-chip memory. The SMC library provides fast design space exploration by allowing the user to specify a target BRAM budget for each SMC, and automatically maps SMC buffers to on and off-chip memory regions. We demonstrate that through the use of the MPack tool and the SMC library, the programmer can quickly generate a range of streaming application memory solutions, and reach performance targets without time consuming manual memory optimization.Ph.D