Co-Locating Code and Data for Energy-Efficient CPUs

The end of Dennard scaling has brought energy savings to the forefront of processor design. When coupled with massive datasets, traditional memory architectures are becoming a source of excess energy expenditure. In this thesis, we propose to conserve energy through the co-location of code and data, which limits data movement on and off the chip. To that end, we design a data prefetcher called Tempo that reduces useless prefetches by 18% and increases timeliness by 43%. Tempo boosts the performance of the state of the art Spatial Memory Streaming prefetcher by up to 20% (2.54% average). In contrast to data prefetching, we also describe an execution paradigm called Anti-Fetching, which dynamically moves code off-chip to a Near-Data Processor. Using Anti-Fetching on a set of graph processing benchmarks provides up to 31% energy savings in the memory hierarchy (11% average) over an efficient CPU baseline.M.A.S