A Voltage Scaling Power Reduction Strategy for Memory-based LDPC Decoders

In baseband digital signal processing, dynamic voltage scaling is an effective method to reduce the power consumption of an SOC. Voltage scaling directly applied to embedded memories can lead to stability issues such as memory read and write errors. This thesis explores the possibility of applying voltage scaling technique to embedded memory that is used in forward error correction circuits (an LDPC decoder), in order to compensate for the error induced by voltage scaling while improving the over energy efficiency of an LDPC decoder. This thesis used an LDPC decoder designed for wireless IEEE802.11ad WiFi standard as a target to quantitatively characterize its inherent tolerance to embedded memory errors. An adaptive voltage scaling control algorithm is then proposed based on the error tolerance model. A hardware aware implementation strategy is also presented with a simulated energy saving potential of up to 20%.M.A.S