Circuits for Blind ADC-based CDRs and Frequency Detectors

This thesis presents three contributions in the area of clock and data recovery (CDR). Two of these three contributions focus on the design of frequency detection mechanisms for reference-less half-rate clock and data recovery circuits, while the third one focuses on the design of blind ADC-based CDRs. While conventional CDR architectures for phase and frequency detection are dual loop, the interaction between the frequency detection loop and the phase detection loop can interfere with phase locking. Furthermore, the frequency detector, typically deactivated after lock, occupies area. This thesis introduces two new architectures for reference-less CDRs which perform frequency detection by adjusting the phase error of the phase detector. This enables the phase detector to deal with frequency offset, as well as phase offset. The feasibility of these two 10Gb/s CDRs are demonstrated through chip fabrications in Fujitsu 65nm CMOS technology and measurement results. The third contribution of this thesis is in the area of blind ADC-based CDRs. While the design simplicity of these CDRs significantly reduces their time to market, their high power consumption limits their application. This thesis studies the architecture of these CDRs with the goal of minimizing their power consumption. We will show that for a given analog power consumption, the optimum oversampling ratio is 2.8 (~3). The digital CDR is also redesigned to lower the power consumption of digital equalization. A 5Gb/s CDR was fabricated in Fujitsu 65nm CMOS technology and measurement results show a factor of 2 of power reduction, with improved performance.Ph.D