A Study of the Potential of Intel's Transactional Synchronization Extensions for Hybrid Transactional Memory

Hardware Transactional Memory (TM) attempts to deliver on the promises made with Software Transactional Memory by enabling scalable parallel execution with low programming effort. Intel's TSX is a recent such effort to provide hardware support for Transactional Memory on commodity hardware. This dissertation studies the limitations of TSX and proposes both manual and automated techniques for improving application parallelism. We find that using only TSX may result in high abort rates and poor performance for certain workloads due to hardware resource limitations. Using the Moldyn benchmark, we present a series of manual optimizations on TSX to achieve performance comparable to fine-grained locking. We then translate the identified manual optimizations into automated techniques in the form of a software-hardware hybrid transactional memory library called HyTM. Using a realistic benchmark, SynQuake, we experimentally show that HyTM can significantly increase the fraction of transactions that take advantage of TSX and execute in hardware.M.A.S