Advances in Debug Automation for a Modern Verification Environment

Over the past three decades, the growing list of requirements for integrated circuits has continually presented new challenges to the electronic design community. One of the biggest challenges in the design process is that of functional debugging, which aims to find the root-cause of a functional failure after it has been detected. In recent years, this key challenge has grown in size and scope as bugs commonly appear in both the design and verification environment. This increase in size and scope has made functional debugging one of the largest bottlenecks in the design cycle and points to an urgent need for more scalable and innovative debugging solutions. This dissertation presents multiple novel contributions that address the challenges of increased size and scope of modern functional debugging. In particular, these contributions address the scalability of existing automated design debugging techniques, as well as introduce novel automated tools specifically for debugging the verification environment. The first contribution introduces an unsatsifiable core-guided abstraction and refinement technique for design debugging that focuses on managing the design size aspect of debugging complexity. The second contribution introduces a path-directed abstraction and refinement technique that aims to manage the error trace length aspect of debugging complexity. The third contribution presents a novel method that utilizes unsatisfiable cores in design debugging to manage the multiple design errors aspect of debugging complexity. The fourth contribution presents an automated technique to aid debugging of errors found within formal properties themselves. The final contribution presents an automated technique to aid debugging of missing assumptions that are needed during verification methodologies that use formal methods.Ph