Exploiting low-latency communication in single-chip multiprocessors

grantor: University of TorontoImplementing multiple processors on a single chip is one of the more promising methods of using increasing numbers of transistors. An important design question is how to provide low-latency communication without imposing overhead on sequential applications. In our study, we compared the performance of a shared primary cache design and shared secondary cache designs using three different cache coherence protocols. Our results for a shared primary cache design showed that the increased latency of the primary cache significantly degraded execution time. In our shared secondary cache design, we found that a directory protocol performed the best in terms of execution time and memory traffic. Finally, we proposed hardware support to implement accelerated updates, locks, and barriers. We simulated these proposals using microbenchmarks to determine how much performance gain they can provide and under what conditions.M.A.Sc