Code compaction for VLIW instructions

grantor: University of TorontoThe VLIW architecture is modular and scalable which makes it suitable for implementing application-specific programmable processors. However, the large instruction storage and bandwidth requirements have prevented VLIW architectures from being used in cost-sensitive systems. This thesis builds upon a novel instruction packing and fetching mechanism developed by previous University of Toronto researchers, by exploring ways to achieve code compaction via improved packing techniques, stack restructuring and register allocation. The improved packing techniques involve transforming an instruction into a more compact-able equivalent instruction and are able to achieve 100% memory utilization and an average of 2.4% size reduction. Stack restructuring focuses on minimizing the unique stack-related constant operands, which in turn minimizes the number of unique operation patterns, leading to a maximum of 16.8% memory size reduction. Finally, live-range recoloring techniques are developed, targeting on minimizing the total unique operation patterns. Unfortunately, there are no significant reductions achieved. Two of the three aspects examined in the thesis are able to further reduce the instruction storage requirement without affecting the execution speed of the program.M.A.Sc