Design and layout of a computational field programmable architecture

grantor: University of TorontoField Programmable Devices (FPDs) are a very popular medium for implementing digital circuits. They offer many positive features such as re-programmability, low design manufacturing cost and fast time to market. Compute intensive applications used in signal and data processing are often implemented in FPDs. A primary reason for this is that FPDs are well suited to extracting the parallelism that often exists in these applications. FPDs are not ideally suited to this task, however, as they cannot efficiently realize common arithmetic structures such as adders, subtracters and multipliers. We have designed and implemented a custom layout for a Field Programmable Architecture that is targeted to compute intensive applications. The architecture, called the CFA, is intended to offer efficient realizations of the arithmetic structures commonly found in compute intensive applications. Preliminary results from our detailed area model show that our architecture is on average 3-4 times more area efficient than conventional FPD architectures on a set of arithmetic circuits.M.A.Sc