Design of a CMOS current conveyor-based field-programmable analog array

grantor: University of TorontoTo date, all published CMOS field-programmable analog array (FPAA) designs have operated under 1MHz bandwidths. This thesis develops circuit methods allowing the development of a CMOS FPAA operating at greater than 1MHz frequencies. For this purpose the second-generation current conveyor (CCII) is used. IC test results of a 0.8$\mu$m CMOS chip containing four configurable analog blocks based on the CCII, as well as an interconnection network based on transmission gates, are presented. The test results show that bandwidths exceed 10MHz. The four CABs and interconnect occupy a core area of $\rm1551.8 \times 741.2\mu m\sp2$. The thesis also proposes an FPAA design based on current conveyors and similar to a commercial bipolar FPAA, but operating at higher bandwidths; as well, a novel voltage comparator based on the CCII is proposed.M.A.Sc