A process for SOI resonators with surface micromachined covers and reduced electrostatic gaps

This paper describes work to fabricate resonators on silicon-on-insulator (SOI) wafers with sub-micron gaps and wafer level encapsulation. Non-aligned, high-temperature fusion bonding of a cover wafer over unreleased structures etched into a SOI wafer is followed by cover wafer stripping to reveal etched resonators beneath an oxide membrane. Reliable bonding is assured by bonding unreleased structures which can withstand the appropriate pre-bond cleaning operations. The bonded oxide membrane serves as the basis of a surface micromachined membrane which incorporates silicon nitride and a porous polysilicon layer to facilitate release and supercritical drying. The cavity pressure is estimated to be in the range of 1 Torr. Encapsulated resonators were also made using a gap reduction process. The process is based on sidewall oxidation of an etched sleeve to reduce the linewidth of the patterned electrostatic gaps by 200 nm before the deep trench etch. Encapsulated and electrically active devices with gaps down to 500 nm were obtained and etched through a 5 µm thick SOI device layer. SEM images showed that gaps of 300 nm could reach through the same thickness, though functional devices were not obtained. In addition, limitations on the anti-notching process limited its use during the trench etch and resulted in severe notch damage