Supporting concurrent memory access and multioperations in moving threads CMPs

Moving threads is a theoretically interesting approach for mapping the computation of an application to chip multiprocessor (CMP) architectures. Instead of moving data read and write requests, extremely lightweight threads are moved between the processor cores. As a consequence, all kinds of cache coherence problems and need for read reply messages are eliminated. Although moving threads architectures in many ways support the same techniques as their moving data counterparts, the existing architectures support exclusive memory access only degrading the performance of the approach by a logarithmic factor in many algorithms with respect to the best moving data architectures. In this paper we propose an architectural technique supporting partial concurrent memory access and multioperations for a class of synchronous moving threads CMPs. Application examples and performance, silicon area, and power consumption evaluations are given