An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm2. The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160 MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37 dB and noise figure of 11 and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply...
A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power ...
Includes bibliographical references.This dissertation focuses on the design and implementation of an...
This paper presents a 7.9 fJ /conversion-step 10-bit 125 MS/s successive approximation register(SAR)...
An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to dig...
An integrated receiver consisting of RF front ends, analog baseband chain with an analog to digital ...
Recent advances in technologies, architectures, and applications of highly-integrated low-power rada...
approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the...
A 60-Channels ADC (Analog to Digital Converter) board for space borne Digital Beam Forming (DBF) Syn...
This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC wo...
This paper presents a fully differential 12-bit SAR ADC developed for high-voltage CMOS sensors. The...
A 12-bit analog-to-digital converter (ADC) addressed to Silicon-Drift Detectors (SDDs) multichannel ...
The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed ...
An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sam...
This paper presents a low power successive approximation register (SAR) ADC and its front-end automa...
\u3cp\u3eThis paper presents a compact 10-b successive approximation register analog-to-digital conv...
A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power ...
Includes bibliographical references.This dissertation focuses on the design and implementation of an...
This paper presents a 7.9 fJ /conversion-step 10-bit 125 MS/s successive approximation register(SAR)...
An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to dig...
An integrated receiver consisting of RF front ends, analog baseband chain with an analog to digital ...
Recent advances in technologies, architectures, and applications of highly-integrated low-power rada...
approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the...
A 60-Channels ADC (Analog to Digital Converter) board for space borne Digital Beam Forming (DBF) Syn...
This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC wo...
This paper presents a fully differential 12-bit SAR ADC developed for high-voltage CMOS sensors. The...
A 12-bit analog-to-digital converter (ADC) addressed to Silicon-Drift Detectors (SDDs) multichannel ...
The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed ...
An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sam...
This paper presents a low power successive approximation register (SAR) ADC and its front-end automa...
\u3cp\u3eThis paper presents a compact 10-b successive approximation register analog-to-digital conv...
A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power ...
Includes bibliographical references.This dissertation focuses on the design and implementation of an...
This paper presents a 7.9 fJ /conversion-step 10-bit 125 MS/s successive approximation register(SAR)...