Multilayer Techniques to Address Parameter Variation

91 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2008.Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This thesis presents a set of variation-aware algorithms for application scheduling and power management. One such power management algorithm, uses linear programming to find the best voltage and frequency levels for each of the cores in the CMP---maximizing throughput at a given power budget.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD