Software and Hardware Support for Data Intensive Computing

100 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007.In the architectural aspect, we propose a Near-Memory Processor (NMP), a heterogeneous architecture that couples on one chip a commodity microprocessor together with a coprocessor that is designed to run well applications that have poor locality or that require bit manipulations. The coprocessor has a blocked-multithreaded narrow in-order core, and supports vector, streaming, and bit-manipulation computation. It has no caches but has exposed, explicitly addressed fast storage. A common set of primitives supports the use of this storage both for stream buffers and for vector registers. We simulated this coprocessor using a set of 10 benchmarks and kernels that are representative of the applications we expect it to be used for. These codes run much faster, with speedups of up to 18 over a commodity microprocessor, and with a geometric mean of 5.8.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD