Low Phase Noise Oscillator Design. A Design Methodology for Improving Performance: Theoretical Analysis, CAD Simulations, and Prototype Building

167 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.This research encompasses theoretical as well as practical aspects in the design of low phase noise LC-tank CMOS RF oscillators. Novel analytical techniques for estimating the periodic steady-state solution, perturbation-projection vector, and phase noise/timing jitter for oscillators are presented. These techniques enable a quantitative estimate of the oscillator phase noise/timing jitter performance from its constituent circuit characteristics with high accuracy. Further, the engineering techniques presented provide insight and quantitative understanding of current-day deep-submicron CMOS LC-tank oscillator design, and serve as a starting point in a design strategy that includes a complete phase noise/timing jitter optimization. The analytical results presented in this work have been verified by extensive CAD simulations using Berkeley Design Automation's advanced RF circuit simulator. A new quadrature phase oscillator architecture which has lower phase noise performance than the leading current day architectures is presented, and its performance is verified with simulations and chip measurements. Fourteen oscillators consisting of 7 voltage-controlled oscillators, 3 oscillators, and 4 quadrature-phase VCOs, as well as a low-noise amplifier, and individual device characterization and cancellation structures were fabricated using Fujitsu Laboratories of America 0.11-mum, 1.2-V CMOS silicon express technology. The chips were successfully tested at the Berkeley Wireless Research Center at the University of California at Berkeley and the performance of five of these oscillators is also presented in this work.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD