Add to ORKG120 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.In addition to ISI, jitter also limits performance in high-speed I/O links. A discrete-time model that comprehends both transmit and receive jitter is presented. Typical I/O channels are shown to amplify high-frequency transmit jitter limiting the performance of equalization and multilevel signaling schemes. Design techniques to mitigate the effect of jitter are also presented.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter a...
Synchronization means the aligning of the significant instants of one signal to the significant inst...
120 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.In addition to ISI, jitter al...
ii iv Today’s high-speed interfaces are limited by the bandwidth of the communication channel, tight...
This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigab...
Performing digital signal processing in continuous time can be advantageous for a number of applicat...
Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
University of Minnesota Ph.D. dissertation. December 2019. Major: Electrical Engineering. Advisor: R...
Increase in the signaling speeds has led to decrease in jitter budget available for the channel to p...
Copyright © 2011 Ahmed Ragab et al. This is an open access article distributed under the Creative Co...
A simple model has been developed to characterize electromagnetic interference induced timing variat...
Abstract: The limitation of the high speed analog to digital converters and synchronization systems ...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter a...
Synchronization means the aligning of the significant instants of one signal to the significant inst...
120 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.In addition to ISI, jitter al...
ii iv Today’s high-speed interfaces are limited by the bandwidth of the communication channel, tight...
This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigab...
Performing digital signal processing in continuous time can be advantageous for a number of applicat...
Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition ...
University of Minnesota Ph.D. dissertation. December 2019. Major: Electrical Engineering. Advisor: R...
Increase in the signaling speeds has led to decrease in jitter budget available for the channel to p...
Copyright © 2011 Ahmed Ragab et al. This is an open access article distributed under the Creative Co...
A simple model has been developed to characterize electromagnetic interference induced timing variat...
Abstract: The limitation of the high speed analog to digital converters and synchronization systems ...
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Compute...
Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter a...
Synchronization means the aligning of the significant instants of one signal to the significant inst...