High-Speed, Low-Power 54-B X 54-B Digital Multiplier Architecture Using Redundant Binary

103 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001.A new architecture for a carry-free multiplier is proposed that focuses on redundant binary (RB) numbers and conversion techniques. By incorporating the Booth algorithm along with RB numbers, a pair of 2's complement input words can be multiplied in RB domain free of carry propagation. Using the proposed equivalent bit conversion algorithm (EBCA), the resulting RB product can be converted to a normal binary (NB) product in constant time regardless of word width. A prototype 54-b x 54-b multiplier is implemented using transmission gate logic circuits to prove the concept and algorithms of the proposed architecture. The proposed multiplier fabricated in 0.35 mum CMOS process is tested to operate at 74 MHz with 3.3 V power supply while consuming 53.4 mW of power. The proposed architecture of the carry-free multiplier is an ideal architectural candidate for low-power, high-speed, portable devices.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD