Circuit architectures for high speed CMOS clock and data recovery circuits

As semiconductor process technologies continue to scale and the demand for ubiquitous computing devices continues to grow with paradigms such as the internet of things (IOT), the availability of low-cost, low-power, high-speed and robust communication interfaces between these devices will be a major challenge that needs to be addressed. Even in traditional desktop computing devices, the off-chip bandwidth does not scale as fast as the on-chip bandwidth and has therefore been an important bottleneck to the growth in processing speed. Thus, intelligent techniques will have to be developed that allow the traditional lossy channels to be deployed at higher data rates, while minimizing cost and power, without paying much of a performance penalty. Over the last decade and a half, a great amount of research has been done to design monolithic transmitter and receiver integrated circuits (ICs) in silicon complementary metal-oxide semiconductor (CMOS) technology as opposed to traditional discrete SiGe, InP technologies owing to the low cost and ease of integration of CMOS technology. A key component of the receiver is the clock and data recovery (CDR) circuit, which extracts the clock from the incoming data stream and samples the data. The performance of the CDR is a major impediment to increasing data rates in a serial communication system. Several CDR architectures have been proposed to ensure that the performance is comparable to traditional discrete SiGe, InP devices. In this thesis, three different CDR circuit architectures are designed in a 180 nm CMOS process with a target data rate of 2 Gbps and compared in terms of performance, power and area. In order to provide a fair comparison, the corresponding channel and transmitter blocks are also designed and the entire serial communication link is simulated. The fundamentals of CDR circuit design are introduced and a complete guide to analysis and design of CDR circuits for high speed serial links is presented. The results of the comparison help to evaluate power, performance and area trade-offs during the design phase and to choose the right architecture for a given application